module RTC_test(clk50m,rst,SW,LEDR0,HEX0,HEX1,HEX2,HEX3);
	input clk50m;
	input [1:0]rst;
	input [7:0]SW;
	output reg LEDR0;
	output [0:6]HEX0,HEX1,HEX2,HEX3;
	reg [25:0]cnt_s;
	reg [15:0]cnt_m;
	reg [7:0]ready;
	reg [3:0]reaction[0:3];
	reg rst_en;
	reg action_en;

	always @(posedge clk50m) begin
		cnt_s <= cnt_s+1'b1;
		cnt_m <= cnt_m+1'b1;
		if(cnt_s == 26'd50000000)
			cnt_s <= 26'd0;
		if(cnt_m == 16'd50000)
			cnt_m<=16'd0;
		if(rst[0]==0) begin
			rst_en<=1'b1;
			cnt_s<=26'b0;
			ready<=8'b0;
			LEDR0<=1'b0;
			action_en <=1'b0;
			reaction[0]<=4'hf;
			reaction[1]<=4'hf;
			reaction[2]<=4'hf;
			reaction[3]<=4'hf;
		end
		else if(rst_en == 1'b1)begin
			if(cnt_s==0)begin
				ready<=ready+1'b1;
					if(ready==SW)begin
						LEDR0<=1'b1;
						rst_en<=1'b0;
						cnt_m<=16'b0;
						action_en<=1'b1;
						reaction[0]<=4'h0;
						reaction[1]<=4'h0;
						reaction[2]<=4'h0;
						reaction[3]<=4'h0;
					end
			end
		end
		else if(action_en ==1'b1)begin
			if(cnt_m==0)begin
				if(reaction[0]==4'h9)begin
					reaction[0]<=4'h0;
						if(reaction[1]==4'h9)begin
							reaction[1]<=4'h0;
								if(reaction[2]==4'h9)begin
									reaction[2]<=4'h0;
										if(reaction[3]==4'h9)begin
												reaction[3]<=4'h0;end
										else
											reaction[3]<=reaction[3]+1'b1;end
								else
									reaction[2]<=reaction[2]+1'b1;end
						else
							reaction[1]<=reaction[1]+1'b1;end
				else
					reaction[0]<=reaction[0]+1'b1;end
			if(rst[1]==1'b0)begin
				rst_en<=1'b0;
				action_en<=1'b0;
				LEDR0<=1'b0;
			end
		end
	end

	show_decode4_7 u1(reaction[0],HEX0);
	show_decode4_7 u2(reaction[1],HEX1);
	show_decode4_7 u3(reaction[2],HEX2);
	show_decode4_7 u4(reaction[3],HEX3);
endmodule

//显示模块
module show_decode4_7(ST,HEX);
	input [3:0]ST;
	output reg[0:6] HEX;

	always @(*) begin
		case(ST)
			4'b0000: HEX=~7'b1111110;
			4'b0001: HEX=~7'b0110000;
			4'b0010: HEX=~7'b1101101;
			4'b0011: HEX=~7'b1111001;
			4'b0100: HEX=~7'b0110011;
			4'b0101: HEX=~7'b1011011;
			4'b0110: HEX=~7'b1011111;
			4'b0111: HEX=~7'b1110000;
			4'b1000: HEX=~7'b1111111;
			4'b1001: HEX=~7'b1111011;
			default: HEX=~7'b0000000;
		endcase
	end
endmodule